Conventionally, various methods of designing integrated circuits configured by disposing a plurality of cells formed per processing function have been disclosed (for example, see Japanese Laid-open Patent Publication No. 2004-335902). When an integrated circuit is designed, to stabilize an operation of the integrated circuit, a capacitor-cell that is formed as a decoupling capacitor is generally disposed between integrated circuits configured of transistors.
In recent years, as the cell-size of integrated circuits due to miniaturization of semiconductor devices has decreased, the per-unit-area capacity of capacitor-cells has become smaller. Thus, it has become difficult to secure decoupling capacity by the capacitor-cells. Accordingly, various counter-measures have been taken to secure the decoupling capacity by the capacitor-cells.
However, the various counter-measures have problems of having to enlarge a chip size, prepare a large separate site, and use a transistor having a large leak current.
More specifically, there is a problem of having to enlarge the chip size to secure a space for disposing a capacitor-cell that is preferable to secure a decoupling capacity.
Further, there is a problem of having to prepare a separate site larger than an ordinary site in which functional parts (functional parts such as a circuit block and a memory in the integrated circuit) constituting the integrated circuit are disposed, for the purpose of disposing the capacitor-cell preferable for securing the decoupling capacity.
Moreover, there is a problem of having to configure the capacitor-cell using a transistor having a large leak current to secure the decoupling capacity, even though such a configuration is a cause of an increase in electric power consumption in the integrated circuit.